Youssef Bendou

Youssef was born in Rabat, Morocco, in 1997.
Starting 2015, he studied for two years under engineering preparatory classes in CPGE Moulay Youssef Rabat, his hometown.
In 2017 he joined the Grenoble Institute of Technology in France to continue his engineering curriculum.
He then enrolled in an M.S. degree in micro and nanotechnology for integrated systems, jointly delivered in 2020 by l’École Polytechnique Fédérale de Lausanne (EPFL) in Switzerland, the Politecnico di Torino (Polito) in Italy, and Grenoble INP (Phelma).
He is currently pursuing a PhD within the company STMicroelectronics in France in collaboration with Université catholique de Louvain in Belgium and Université de Lille in France, on the design of mm-wave integrated circuits on the 28nm FDSOI technology benefiting from the advantages of high resistivity substrates.


Research Projects

  • mm-wave IC design
  • CAD design and simulations
  • On-wafer measurements


  • Silicon-based substrate modelling and development
      • RF-SOI: High Resistivity and Trap-Rich
      • PN junction-enhanced RF-Si substrates