Lucas was born in Ottignies, Belgium, in 1993. He received the B.S and M.S. degrees in electrical engineering from Université catholique de Louvain, Louvain-la-Neuve, Belgium, in 2014 and 2017, respectively. He also received the M.S. in electronic engineering from Politecnico di Torino, Turin, Italy, in 2017.
He is currently pursuing a Ph.D. degree in electrical engineering at Université catholique de Louvain. His research focuses on the characterization and modelling of passive structures and MOSFETs on SOI technology at millimeter-wave frequencies, towards material properties extraction and device figures of merit assessment. It also includes circuit design to analyze substrate related performance and features at circuit level. His research involves as well advanced on-wafer calibration and de-embedding techniques for accurate characterization at millimeter-wave and sub-millimeter-wave frequencies.
- Ultra-wideband characterization and model extraction of advanced FD-SOI MOSFET
- Advanced Self-Heating characterization
- Substrate and Back-Gate networks modelling
- mm-wave IC design
- 28 GHz switches
- 39 GHz LNA
- On-wafer RF & mm-wave measurements
- RF material property extraction
- Silicon-based substrate modelling and development
- RF-SOI: High Resistivity and Trap-Rich
- PN junction-enhanced RF-Si substrates
- Gold-doped Si
- GaN on Si
- Porous Silicon
- M. Rack, D. Lederer, L. Nyssens, A. Paganini, M. B. Shinde, A. Beganovic and J.-P. Raskin, “Device layout dimension impact on substrate effective resistivity”, 2018 S3S Conference,San Francisco, CA, Oct. 2018, pp. 1-2, doi: 10.1109/S3S.2018.8640211.
- L. Nyssens, M. Rack and J.-P. Raskin, “New method for accurate transmission line characterization on low-loss silicon substrate at millimeter-wave frequencies”, Microwave Technology and Techniques Workshop, ESA-ESTEC, Noordwijk, The Netherlands, Apr.2019.
- M. Rack, L. Nyssens and J.-P. Raskin, “Silicon-substrate enhancement technique enabling high-quality integrated RF passives”, 2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, June 2019, pp. 1295-1298, doi: 10.1109/MWSYM.2019.870109.
- G. Scheen, R. Tuyaerts, M. Rack, L. Nyssens, J. Rasson and J.-P. Raskin, “Post-process local porous silicon integration method for RF application”, 2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, June 2019, pp. 1291-1294, doi: 10.1109/MWSYM.2019.8700844.
- G. Scheen, R. Tuyaerts, M. Rack, L. Nyssens, J. Rasson and J. Raskin, “Post-process porous silicon for 5G applications,” 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Grenoble, France, 2019, pp. 1-2, doi: 10.1109/EUROSOI-ULIS45800.2019.9041906. Award: Best Paper.
- L. Nyssens, M. Rack and J. Raskin, “Effective Resistivity Extraction of Low-Loss Silicon Substrate at Millimeter-Wave Frequencies,” 2019 14th European Microwave Integrated Circuits Conference (EuMIC), Paris, France, 2019, pp. 1-4, doi: 10.23919/EuMIC.2019.8909575. Award: Best Student Paper.
- A. Halder, L. Nyssens, M. Rack, J.-P. Raskin and V. Kilchytska, “Effect of Heat Sink in Back-End of Line on Self-Heating in 22nm FDSOI MOSFETs”, EuroSOI-ULIS, Caen,France, March 2020, pp. xx-yy.
- M. Rack, L. Nyssens, … , and J.-P. Raskin, “DC-40 GHz SPDTs in 22 nm FD-SOI and Back-Gate Impact Study”, Radio Frequency Integrated Circuits Symposium (RFIC), Los Angeles, USA, June 2020, pp. xx-yy.
- L. Nyssens, A. Halder, B. K. Esfeh, N. Planes, D. Flandre, V. Kilchytska and J.-P. Raskin, “28 FDSOI RF Figures of Merit down to 4.2 K,” in Proceedings of the 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
- L. Nyssens, A. Halder, …, J.-P. Raskin, V. Kilchytska, “Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures,” ESSDERC 2019 – 49th European Solid-State Device Research Conference (ESSDERC), Cracow, Poland, 2019, pp. 162-165.
- V. Kilchytska, S. Makovejev, B. Kazemi Esfeh, L. Nyssens, A. Halder, J.-P. Raskin, D. Flandre, “Electrical characterization of advanced MOSFETs towards analog and RF applications,” 2020 IEEE Latin America Electron Devices Conference (LAEDC), San Jose, Costa Rica, 2020, pp. 1-4.
- N. André, M. Rack, L. Nyssens, C. Gimeno, D. Oueslati, K. Ben Ali, S. Gilet, C. Craeye, J.-P. Raskin and D. Flandre, “Ultra Low-Loss Si Substrate for On-Chip UWB GHz Antennas”, IEEE Journal of the Electron Devices Society, vol. 7, pp. 393-397, Mar. 2019, doi: 10.1109/JEDS.2019.2902636.
- M. Rack, L. Nyssens, and J.-P. Raskin, “Low-loss Si-substrates enhanced using buried PNjunctions for RF applications”, IEEE Electron Device Letters, vol. 40, pp. 690-693, May 2019, doi: 10.1109/LED.2019.2908259.
- G. Scheen, R. Tuyaerts, M. Rack, L. Nyssens, J. Rasson, M. Nabet and J.-P. Raskin, “Post-process porous silicon RF 5G applications”, Solid-State Electronics, vol. 168, pp. 107719, ISSN 0038-1101, 2020, doi: 10.1016/j.sse.2019.107719.
- L. Nyssens, M. Rack and J.-P. Raskin, “Effective Resistivity Extraction of Low-Loss Silicon Substrate at Millimeter-Wave Frequencies”, International Journal of Microwave and Wireless Technologies, vol. 12, no. 7, pp. 615-628, 2020, doi: 10.1017/S175907872000077X.
- L. Nyssens, A. Halder, B. K. Esfeh, N. Planes, D. Flandre, V. Kilchytska and J.-P. Raskin, “28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K,” in IEEE Journal of the Electron Devices Society, vol. 8, pp. 646-654, 2020, doi: 10.1109/JEDS.2020.3002201.
- L. Nyssens, A. Halder, B. Kazemi Esfeh, N. Planes, D. Flandre, V. Kilchytska and J.-P. Raskin, “Self-Heating in FDSOI UTBB MOSFETs at Cryogenic Temperatures and its Effect on Analog Figures of Merit,” in IEEE Journal of the Electron Devices Society, vol. 8, pp. 789-796, 2020, doi: 10.1109/JEDS.2020.2999632.