Dimitri Lederer

Dimitri Lederer  received the M.S. and Ph.D. degrees in applied sciences from Université catholique de Louvain (UCLouvain), Louvain-la-Neuve, Belgium, in 2000 and 2006, respectively.

After completing his PhD he worked in various SMEs and large-scale companies on the development of RF & microwave and mmWave products. His last role prior to joining UCLouvain was of Senior Engineer at GlobalFoundries, where he worked on the development of the 45RFSOI technology. 

His research interests cover the modeling, fabrication and characterization of mmWave Si-based devices and circuits.  These research activities also include the integration of III-V and more exotic materials on Si for THz applications. 

 

Research Projects

  • mm-wave IC design
      • 28 GHz switches
      • 39 GHz LNA
  • on-wafer (sub-)-mmWave characterization

 

 
  • Silicon-based waveguide for low loss on-chip signal propagation
    •  
  • III-V material integration on Si for THz applications

Selected publications

Conference Proceedings

  1. M. Rack, L. Nyssens, S. Wane, S. Bajon, D. Lederer, J.-P. Raskin, FD-SOI mm-Wave Differential Single-Pole Switches with Ultra-High Isolation, 2021 VLSI-TSA.
  2. S. Syed, S. Jain, D. Lederer, W. Liu, E. Veeramani , B. Chandhoke, A. Kumar, G. Freeman, “A highly rugged 19 dBm 28GHz PA using novel PAFET device in 45RFSOI technology achieving peak efficiency above 48%,” 2020 IEEE/MTT-S International Microwave Symposium (IMS), Los Angeles, CA, USA, 2020, pp. 1003-1006.
  3. D. Lederer, S. Jain, S. Saroop, A. Kumar and G. Freeman, “45nm PD SOI FET gate resistance optimization for mmw applications,” 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 2018, pp. 1-3.
  4. M. Rack, L. Nyssens, J. -P. Raskin,  D. Lederer, A. Paganini, M. B. Shinde; A. Beganovic, “Device layout dimension impact on substrate effective resistivity,” 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 2018, pp. 1-2.
  5. T. Waliwander, M. Crowley, M. Fehilly, D. Lederer, J. Pike, L. Floyd and D. O’Connell., “Sub-millimeter wave 183 GHz and 366 GHz MMIC membrane sub-harmonic mixers“, 2011 IEEE MTT-S International Microwave Symposium, Baltimore, MD, 2011, pp. 1-4.
  6. J. Pike, L. Floyd, D. O’Connell, T. Waliwander, M. Crowley and D. Lederer, “Schottky membrane technology for sub-mm wave applications“, The 5th European Microwave Integrated Circuits Conference, Paris, 2010, pp. 222-225.
  7. J. Pike, L. Floyd, D. O’Connell, K. Thomas, A. Olsen, and D. Lederer, “Development of a Novel 380GHz Membrane Subharmonic Mixer“,5th ESA Workshop on Millimetre Wave Technology and Applications, ESTEC, Noordwijk, May 2009.
  8. D. Lederer, Schottky technology for submillimeter-wave radiometric applications (invited paper), “THz Radiation: Basic Research and Applications” 2008 Workshop, October, Alushta, Ukraine.
  9. D. Lederer, C. Desrumeaux, F. Brunier and J.-P. Raskin, “High Resistivity SOI substrates: how high should we go?“, 2003 IEEE International SOI Conference, Newport Beach (CA), Sept. 2003, pp. 50-51.
  10. D. Lederer, R. Lobet and J.-P. Raskin, “Enhanced High resistivity SOI wafers for RF applications“, 2004 IEEE International SOI Conference, Charleston (SC), Oct. 2004, pp. 46-47.
  11.   D. Lederer, V. Kilchytska, T. Rudenko N. Collaert, D. Flandre, A. Dixit, K. De Meyer and J.-P. Raskin, “FinFET analog characterization from DC to 110 GHz“, EUROSOI Workshop, Grenada, Spain, January 2005, pp.99-100.

     

Journal Papers

  1. C. RodaNeve, V. Kilchytska, J. Alvaro, D. Lederer, O. Militaru, D. Flandre, J.-P. Raskin, Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer, Microelectronics Reliability Journal, vol.51(2), Feb. 2011, pp. 326-331.
  2.  J.-P. Raskin, G. Pailloncy, D. Lederer, F. Danneville, G. Dambrine, S. Decoutere, A. Mercha and B. Parvais, High Frequency Noise Performance of 60 nm gate length FinFETs, IEEE Trans. Electron Dev., vol.55(10), Oct. 2008, pp.2718-2727.
  3. D. Lederer and J.-P. Raskin, RF performance of an industrial SOI technology transferred onto a passivated HR silicon substrate, IEEE Trans. Electron Dev., 55, vol. 7, pp. 1664-1671, July 2008.
  4. D. Lederer and J.-P. Raskin, Characterization of body node in PD SOI MOSFETs using multiport VNA measurements, IEEE Trans. Electron Dev., 54 (11), Nov. 2007, pp. 3030-3039.
  5. V. Kilchytska, G. Pailloncy, D. Lederer, J.-P. Raskin, N. Collaert, M. Jurczak, D. Flandre, Frequency variation of the small-signal output conductance of decananometer MOSFETs due to substrate crosstalk, IEEE Electron Dev. Lett., 28 (5), May 2007, pp. 219-221.
  6.  D. Lederer and J.-P. Raskin, On-wafer wideband electrical characterization: a powerful tool for improving the IC technologies, (invited paper), Journal of Telecommunications and Information Technology, no. 2, pp. 69-77, 2007.
  7. M. Si Moussa, C. Pavageau , D. Lederer, L. Picheta, F. Danneville, N. Fel,  J. Russat, J.-P. Raskin and D. Vanhoenacker-Janvier, Behaviour of TFMS and CPW Line on SOI Substrate versus High Temperature for RF Applications, Solid State Electronics, 50, 2006, pp. 1822-1827. 
  8.  J.-P. Raskin, T. M. Chung, V. Kilchytska, D. Lederer and D. Flandre, Analog/RF Performance of Multiple-gate SOI Devices: Wideband Simulations and Characterization, IEEE Trans. Electron Dev., 53(5), 2006, pp. 1088-1095.
  9.   V. Kilchytska, D. Lederer, P. Simon, N. Collaert, J.-P. Raskin and D. Flandre, Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: suppression of the influence of floating-body effects, IEEE Electron Dev. Lett., 26(10), 2005, pp. 749-752. 
  10. D. Lederer, V. Kilchytska, T. Rudenko, N. Collaert, D. Flandre, A. Dixit, K. De Meyer and J.-P. Raskin, FinFET analogue characterization from DC to 110 GHz, Solid State Electronics, 49(9), 2005, pp 1488-1496.
  11. D. Lederer and J.-P. Raskin, New Substrate Passivation Technique Dedicated to High Resistivity SOI Wafer Fabrication, IEEE Electron Dev. Lett., 26(11), 2005, pp. 805-807. 
  12.  D. Lederer, D. Flandre and J.-P. Raskin, Frequency degradation of SOI MOS device output conductance, Semiconductor and Science Technology, vol.20 (5), 2005, pp. 469-472.
  13.  D. Lederer and J.-P. Raskin, Effective resistivity of fully-processed SOI substrates, Solid State Electronics, vol 49 (3), 2005, pp. 491-496. 
  14. D. Lederer, D. Flandre and J.-P. Raskin, AC behavior of gate-induced floating body effects in ultra-thin oxide PD SOI MOSFETs, IEEE Electron Dev. Lett., Feb 2004, pp. 104-106.
  15. D. Lederer and J. P. Raskin, Substrate Loss Mechanisms for Microstrip and CPW Transmission Lines on Lossy Silicon Wafers, Solid State Electronics, vol. 47, 2003, pp. 1927-1936.

Book Chapters

  1. J.-P. Raskin, D. Lederer, V. Kiltchytska and D. Flandre, Wideband Characterization of SOI materials and devices, in ‘Solid State Electronics Research Trends’, Nova Publisher, 2009.

  2. V. Kilchytska, D. Levacq, D. Lederer, G. Pailloncy, J.-P. Raskin and D. Flandre, “Substrate effect on the output conductance frequency response of SOI MOSFETs”, (invited paper), in “Nanoscaled Semiconductor-on-Insulator Structures and Devices”, S. Hall, A.N. Nazarov, V.S. Lysenko (eds), Kluwer Academic Publishers, pp. 221-238, 2007, ISBN 978-1-4020-6379-4.

  3. D. Lederer and J.-P. Raskin, Temperature dependence of RF losses in HR SOI substrates, in “Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment”, Flandre D., Nazarov A.N., Hemment P.L.F. (Eds), Kluwer Academic Publ. -NATO Science Series Elsevier, 2005, pp. 192-196.

Patents

  1. D.Lederer, Bartlomiej Pawlak, Charge-Trapping Layers For III-V Semiconductor Devices, filed in April 2020, USA.  

  2. D. Lederer, Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses, PCT/BE2004/000137, filed in October 2004, United States Patent Application: 20070032040.

  3.  J.-P. Raskin, D. Lederer and F. Brunier, Process for manufacturing a multilayer structure made from semiconducting materials,
    filed in March 2006, United States Patent Application: US 7585748 B2