Dr. Martin Rack

Martin’s main interests are substrate modeling, characterization and optimization towards successful monolithic integration of RF devices using silicon technology.

To that end he is involved in the complete small-signal modeling of large substrate volumes for the evaluation of substrate crosstalk interference between circuit nodes.

On top of that, he is also actively developing large-signal models of the non-linear behavior of semiconductor substrate interfaces for the evaluation of substrate-induced harmonic distortion in RF systems.

He is also working on the IC design of RF and mm-wave front-end modules using advanced FD-SOI CMOS nodes, including switches, low-noise amplifiers and mixers, in particular at 28 and 60 GHz.

Research Projects

  • Non-linear large-signal RF substrate modelling
  • mm-wave IC design
      • SPDT and SP4T switches (up to 80 GHz)
      • LNAs (28, 39, 60 GHz)
  • On-wafer RF & mm-wave measurements
  • RF material property extraction


  • Silicon-based substrate modelling and development
      • RF-SOI: High Resistivity and Trap-Rich
      • PN junction-enhanced RF-Si substrates
      • Gold-doped Si
      • GaN on Si
      • Porous Silicon

Publications                   link to full list

Selected Conference Proceedings

  1. M. Rack, L. Nyssens and J.-P. Raskin, “Silicon-substrate enhancement technique enabling high-quality integrated RF passives”, 2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, June 2019, pp. 1295-1298, doi: 10.1109/MWSYM.2019.870109.
  2. G. Scheen, R. Tuyaerts, M. Rack, L. Nyssens, J. Rasson and J. Raskin, “Post-process porous silicon for 5G applications,” 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Grenoble, France, 2019, pp. 1-2, doi: 10.1109/EUROSOI-ULIS45800.2019.9041906. Award: Best Paper.
  3. M. Rack, L. Nyssens, S. Wane, D. Bajon and J.-P. Raskin,DC-40 GHz SPDTs in 22 nm FD-SOI and Back-Gate Impact Study”, Radio Frequency Integrated Circuits Symposium (RFIC), Los Angeles, USA, June 2020, pp. xx-yy, doi: 10.1109/RFIC49505.2020.9218317.
  4. M. Rack, L. Nyssens, S. Wane, D. Bajon, D. Lederer and J. -P. Raskin, “FD-SOI mm-Wave Differential Single-Pole Switches with Ultra-High Isolation,” 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021, pp. 1-2, doi: 10.1109/VLSI-TSA51926.2021.9440095.
  5. M. Rack, L. Nyssens, D. Lederer, Q. Courte, and J.-P. Raskin, “Impact of Device Shunt Loss on mm-Wave Switch Performance in 22 nm FD-SOI and DC-80 GHz SPDT”, in ESSDERC 2021 – 51st European Solid-State Device Research Conference (ESSDERC), 2021, doi: .
  6. M. Rack, L. Nyssens, M. Nabet, and D. L. J.-P. Raskin, “Field-Effect Passivation of Lossy Interfaces in High-Resistivity RF Silicon Substrates”, 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Sep. 2021, doi: .

Selected Journal Papers

  1. M. Rack, F. Allibert, J.-P. Raskin, “RF modelling of trap-rich passivated semiconductor substrates: Part I – Static and dynamic physics of carriers and traps”, IEEE Transactions on Electron Devices, 2021, doi: 10.1109/TED.2021.3096777.
  2. M. Rack, F. Allibert, J.-P. Raskin, “RF modelling of trap-rich passivated semiconductor substrates: Part II – Parameter impact on harmonic distortion”, IEEE Transactions on Electron Devices, 2021, doi: 10.1109/TED.2021.3096781.
  3. B. Kazemi Esfeh, M. Rack, S. Makovejev, F. Allibert and J.-P. Raskin, “A SPDT RF Switch Small-and Large-signal Characteristics on TR-HR SOI Substrates”, IEEE Journalof the Electron Devices Society, vol. 6, pp. 543-550, Feb. 2018, doi: 10.1109/JEDS.2018.2805780.
  4. M. Rack, Y. Belaroussi, K. B. Ali, G. Scheen, B. K. Esfeh and J. P. Raskin, “Small-and Large-Signal Performance Up To 175◦C of Low-Cost Porous Silicon Substrate for RF Applications”, IEEE Trans. Electron Devices, vol. 65, no. 5, pp. 1887-1895, May 2018, doi: 10.1109/TED.2018.2818466.
  5. M. Rack, L. Nyssens, and J.-P. Raskin, “Low-loss Si-substrates enhanced using buried PN junctions for RF applications”, IEEE Electron Device Letters, vol. 40, pp. 690-693, May 2019, doi: 10.1109/LED.2019.2908259.
  6. M. Nabet, M. Rack, Nur Zatil Ismah Hashim, C. H. de Groot, and J.-P. Raskin, “Behavior of Gold-Doped Silicon under Small- and Large-RF Signal”, Solid-State Electronics, vol. 168, pp. 107718, ISSN 0038-1101, 2020, doi: 10.1016/j.sse.2019.107718.
  7. M. Rack and J.-P. Raskin, “(Invited) SOI Technologies for RF and Millimeter Wave Applications”, Electrochemical Society (ESC) Transactions, vol. 92, no. 4, pp 79-94, July 2019, doi: 10.1149/09204.0079ecst.
  8. L. Nyssens, M. Rack and J.-P. Raskin, “Effective Resistivity Extraction of Low-Loss Silicon Substrate at Millimeter-Wave Frequencies”, International Journal of Microwave and Wireless Technologies, pp. 1-14, 2020, doi: 10.1017/S175907872000077X.

Book Chapters

  1. X. Sun, M. Rack, G. Van der Plas, J.-P. Raskin and E. Beyne, “Modeling and Characterization of TSV Induced Noise Coupling”, in “Noise Coupling in System-on-Chip”, 1st ed., T. Noulis, Ed. Boca Raton: CRC Press, 2017, pp. 195-232, ebook ISBN: 9781315116693.
  2. M. Rack and J.-P. Raskin, “SOI Technology for RF and Millimeterwave Applications” in”Intelligent Nanosystems”, 1st ed., vol. 4, S. Deleonibus, Ed. Singapour, Pan Stanford Publishing, 2020, (awaiting publication).


  1. M. Broekaart, F. Allibert, E. Desbonnet, J.-P. Raskin and M. Rack, “Procédé Pour Minimiser une Distorsion d’un Signal dans un Circuit Radiofréquence”, FR3066858, 30 Nov. 2018.
  2. M. Rack and J.-P. Raskin, “Integrated Circuit Device and Method of Manufacturing Thereof”, WO2019211412, 7 Nov. 2019.