Thibault Fiasse was born in Etterbeek, Belgium, in 2001, and received his B.S. and M.S. degrees in electrical engineering from Université catholique de Louvain in 2022 and 2024, respectively. He is currently a PhD student at the electrical engineering department at UCLouvain.

His research focuses on the post-process porosification of standard silicon substrate towards integration with the bulk CMOS industry in close collaboration with Incize, Louvain-La-Neuve, Belgium.

His work includes characterization of RF passives structures, physics-based simulation of semiconductor materials and (clean-room) process optimization.