Dr. Massinissa Nabet

Massinissa Nabet was born on the 20th of April 1993 in the Bejaîa province, Algeria. He got his Bsc degree in Electrical Engineering in 2014, then the master degree in Electronic Systems Instrumentation in 2016 from Université des Sciences et de la Technologie Houari Boumediène, Algiers, Algeria. He received his PhD degree from Université catholique de Louvain (UCLouvain), Ottignies-Louvain-la-Neuve, Belgium, in 2025 entitled “Enhanced high-resistivity silicon-based substrates for RF and mmWave FD-SOI circuits”.

His research focus on substrate modeling and high-frequency characterization of RF devices, including passive components such as CPW lines, inductors, combiners, crosstalk structures, baluns, and filters in Silicon-on-Insulator (SOI) technology.

His work encompasses comprehensive small- and large-signal characterization of advanced Fully-Depleted (FD) SOI transistors and circuit modules. Additionally, he contributes to RF Front-End Module (FEM) circuit design, with expertise in designing RF mixers, high power RF switches, and wideband power amplifiers.

Research Projects

  • mm-wave IC design
      • 28 GHz mixer design
      • High-Power sub-6 GHz RF switches
      • Wideband power amplifier
  • On-wafer RF & mm-wave measurements
      • DC-170 GHz
      • 20°C to 200°C
      • Large-signal RF power measurements up to 50 dBm

  • Silicon-based substrate modelling and development
      • RF-SOI: High Resistivity and Trap-Rich
      • Gold-compensated Si substrates for RF applications
      • PN junction-enhanced RF-Si substrates
  • Physical small- and large-signal modelling of RF substrates

Publications

Conference Proceedings

  1. M. Nabet, M. Rack, Nur Zatil Ismah Hashim, C. H. de Groot, and J. -P. Raskin, “Behavior of Gold-Doped Silicon under Small- and Large-RF Signal”, Fifth Joint International EUROSOI-ULIS Conference on SOI and Ultimate Integration on Silicon – EuroSOI-ULIS 2019“, Grenoble, France.
  2. Q. Courte, M. Rack, M. Nabet, P. Cardinael and J. -P. Raskin, “High-Temperature Characterization of Novel Silicon-Based Substrate Solutions for RF-IC Applications,” ESSDERC 2021 – IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021.
  3. M. Rack, L. Nyssens, M. Nabet, D. Lederer and J. -P. Raskin, “Field-Effect Passivation of Lossy Interfaces in High-Resistivity RF Silicon Substrates,” 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), 2021.
  4. M. Moulin, M. Rack, T. Fache, M. Nabet, Z. Chalupa, C. Plantier, F. Allibert, F. Gaillard, J. Lugo, L. Hutin and J. -P. Raskin, “Nox and Buried PN junctions effect on RF performance of High-Resistivity Silicon substrates,” 2022 IEEE 22nd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2022.
  5. I. Bertrand, P. Flatresse, G. Besnard, J.-M. Bethoux, Z. Chalupa, C. Plantier, M. Rack, M. Nabet, J. -P. Raskinand F. Allibert, “Development Of High Resistivity FD-SOI Substrates for mmWave Applications,” in ECS Transactions, 2022.
  6. M. Rack, L. Nyssens, M. Nabet, C. Schwan, Z. Zhao, S. Lehmann, T. Herrmann, D. Henke, A. Kondrat, C. Soonekindt, F. Koch, T. Kache, D. P. Kini, O. Zimmerhackl, F. Allibert, C. Aulnette, D. Lederer and J. -P. Raskin, “High-Resistivity Substrates with PN Interface Passivation in 22 nm FD-SOI“, in 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, 2022, pp. 1-2, doi: 10.1109/VLSI-TSA54299.2022.9771028.
  7. M. Nabet, M. Rack, L. Nyssens, J. -P. Raskin and D. Lederer, “28 GHz Down-Conversion Mixer with RF Back-Gate Excitation Topology in 22-nm FD-SOI“, in 17th European Microwave Integrated Circuits Conference (EuMIC), Milan, Italy, 2022, pp. 296-299, doi: 10.23919/EuMIC54520.2022.9923503.
  8. L. Nyssens, M. Rack, M. Nabet, C. Schwan, Z. Zhao, S. Lehmann, T. Herrmann, D. Henke, A. Kondrat, C. Soonekindt, F. Koch, T. Kache, D. P. Kini, O. Zimmerhackl, F. Allibert, C. Aulnette, D. Lederer, J.-P. Raskin,”PN Junctions Interface Passivation in 22 nm FD-SOI for Low-Loss Passives“, 2022 24th International Microwave and Radar Conference (MIKON), 2022, pp. 222-224.
  9. Y. Huang, Y. Yan, M. Nabet, F. Liu, B. Li, B. Li, Z. Han, B, -Y, Nguyen, S. Cristoloveanu, J. -P. Raskin, “C-V Measurement and Modeling of Double-BOX Trap-Rich SOI Substrate“, in 9 th Joint Intl EuroSOI Workshop and International Conf On Ultimate Integration on Silicon 2023“, Tarragona, Spain (from 10/05/2023 to 12/05/2023).
  10. M. Nabet, M. Rack, B. Huet, R. Tuyaerts, G. Scheen, L.-Y. Zhang, A. Emiel, C. Dorion, P. Blondy, R. Stefanini, J. -P. Raskin, “High Resistivity Trap-Rich Substrate for RF MEMS Switches“, 2023 Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS (DTIP), Valetta, Malta, 2023, pp. 1-4, doi: 10.1109/DTIP58682.2023.10267954.
  11. G. Scheen, R. Tuyaerts, P. Cardinael, E. Ekoga, K. Aouadi, C. Pavageau, A. Rassekh, M. Nabet, S. Yadav, J.-P. Raskin, B. Parvais, M. Emam, “GaN-on-Porous Silicon for RF Applications“, 2023 53rd European Microwave Conference (EuMC), Berlin, Germany, 2023, pp. 842-845, doi: 10.23919/EuMC58039.2023.10290465.
  12. S. Ma, M. Nabet, R. Hanus, J.-P Raskin, L. Francis and D. Lederer. “Towards Porous SI THz Planar Waveguides in Ultra-Low-Resistivity Substrates“. In 2024 15th Global Symposium on Millimeter-Waves & Terahertz (GSMM) (pp. 225-227). IEEE.
  13. M. Rack, M. Nabet, Y. Bendou, M. Vanbrabant, M. Moulin, Q. Courte, S. Cremer, A. Cathelin, D. Lederer, and J.- P. Raskin, “Low-Loss Silicon Substrates with PN Passivation in 28 nm FD-SOI,” in Tenth Joint International EUROSOI-ULIS Conference on SOI and Ultimate Integration on Silicon-EuroSOI-ULIS 2024, 2024.
  14. Y. Yan, M. Rack, M. Vanbrabant, M. Nabet, A. Goebel, P. Clifton, J.-P. Raskin, “Traps Characterization in RF SOI Substrates Including a Buried SiGe Layer,” in Tenth Joint International EUROSOI-ULIS Conference on SOI and Ultimate Integration on Silicon-EuroSOI-ULIS 2024, 2024.
  15. M. Nabet, M. Rack, S. Crémer, F. Paillardet, A. Cathelin, J.- P. Raskin, and D. Lederer, “Sub-6 GHz RF SPDT Switches Designed in an Advanced 28 nm Fully-Depleted Silicon-on-Insulator Technology with a High Resistivity Substrate,” in 2024 19th European Microwave Integrated Circuits Conference (EuMIC), 2024, pp. 455–458.

Journal Papers

  1. M. Nabet, M. Rack, Nur Zatil Ismah Hashim, C. H. de Groot, and J.-P. Raskin, “Behavior of Gold-Doped Silicon under Small- and Large-RF Signal”, Solid-State Electronics, vol. 168, pp. 107718, ISSN 0038-1101, 2020, doi: 10.1016/j.sse.2019.107718.
  2. G. Scheen, R. Tuyaerts, M. Rack, L. Nyssens, J. Rasson, M. Nabet and J.-P. Raskin, “Post-process porous silicon RF 5G applications”, Solid-State Electronics, vol. 168, pp. 107719, ISSN 0038-1101, 2020, doi: 10.1016/j.sse.2019.107719.M
  3. E. Vandermolen, P. Ferrandis, F. Allibert, M. Nabet, M. Rack, J. -P. Raskin and M. Cassé, “Characterization and role of deep traps on the radio frequency performances of high resistivity substrates,” in Journal of Applied Physics (JAP), vol. 129, 2021, doi : https://doi.org/10.1063/5.0045306.
  4. Q. Courte, M. Rack, M. Nabet, P. Cardinael and J. -P. Raskin, “High-Temperature Characterization of Multiple Silicon-Based Substrate for RF-IC Applications“, in IEEE Journal of the Electron Devices Society, vol. 10, pp. 620-626, 2022, doi: 10.1109/JEDS.2022.3188893.
  5. L. Nyssens, M. Rack, M. Nabet, C. Schwan, Z. Zhao, S. Lehmann, T. Herrmann, D. Henke, A. Kondrat, C. Soonekindt, F. Koch, T. Kache, D. P. Kini, O. Zimmerhackl, F. Allibert, C. Aulnette, D. Lederer, J.-P. Raskin, “High-Resistivity with PN Interface Passivation in 22 nm FD-SOI technology for Low-Loss Passives at RF and Millimeter-Wave Frequencies“, in Solid State Electronics, vol. 205, pp. 108656, ISSN 0038-1101, April 2023, doi: https://doi.org/10.1016/j.sse.2023.108656.
  6. M. Nabet, M. Rack, Y. Yan, B. -Y. Nguyen and J. -P. Raskin, “Double Buried Oxide Trap-Rich Substrates for High Frequency Applications“, in IEEE Electron Device Letters, vol. 44, no. 4, pp. 570-573, April 2023, doi: 10.1109/LED.2023.3243693.
  7. Y. Huang, Y. Yan, M. Nabet, F. Liu, B. Li, B. Li, Z. Han, S. Cristoloveanu, J.-P. Raskin, “C-V Measurement and Modeling of Double-BOX Trap-Rich SOI Substrate“, in Solid-State Electronics, vol. 168, pp. 107718, ISSN 0038-1101, September 2023, doi: https://doi.org/10.1016/j.sse.2023.108763.
  8. Y. Huang, Y. Yan, M. Nabet, F. Liu, B. Li, B. Li, Z. Han, S. Cristoloveanu, J.-P. Raskin, “Analysis of anomalous C-V behavior for extracting the traps density in the undoped polysilicon with a double-BOX structure“, in Solid-State Electronics, vol. 168, pp. 108946, ISSN 0038-1101, 2024, doi: https://doi.org/10.1016/j.sse.2024.108946.
  9. Y. Huang, F. Liu, S. Cristoloveanu, S. Ma, M. Nabet, Y. Yan, B. Li, B. Li, B.-Y. Nguyen, Z. Han, J.-P. Raskin, “C-V characterization of the trap-rich layer in a novel Double-BOX structure“, in Solid-State Electronics, vol. 168, pp. 108951, ISSN 0038-1101, 2024, doi: https://doi.org/10.1016/j.sse.2024.108951.
  10. [10] L. Nyssens, M. Nabet, M. Rack, Y. Bendou, S. Wane, J. Sombrin, J.- P. Raskin, and D. Lederer, “Analysis of Back-Gate Bias Control on EVM Measurements of a Dual-Band Power Amplifier in 22 nm FD-SOI for 5G 28 and 39 GHz Applications,” IEEE Transactions on Circuits and Systems, vol. 44, no. 4, pp. 570–573, 2024, doi: 10.1109/TCSI.2024.3487636.

Book Chapters

  1. M. Rack, L. Nyssens, M. Nabet, D. Lederer, J. -P. Raskin, “Impact of High-Resistivity Substrate on RF and mm-Wave Performance of 22 nm FD-SOI Devices and Circuits“, in “Technologies Enabling Future Mobile Connectivity & Sensing” (1st ed.) River Publishers: Computer Science, Engineering & Technology. ebook ISBN: 9781032633039. https://doi.org/10.1201/9781032633039.