Lucas Nyssens

Lucas was born in Ottignies, Belgium, in 1993. He graduated in two M.S. degrees in 2017, namely Electronic Engineering from Politecnico di Torino, Turin (Italy), and in Electrical Engineering from Université catholique de Louvain, Louvain-la-Neuve (Belgium). In 2023, he completed a 5-years-long Ph.D. degree in Electrical Enginering at Université catholique de Louvain, on the broad topic of Silicon-On-Insulator (SOI) technology at radiofrequency and millimeter-wave technologies. He has written 15 peer-reviewed papers in periodicals and conferences, and 2 book chapters as first author. He was awarded in 2020 the best young engineer paper prize at EuMIC.

His research focuses on the characterization and modelling of passive structures and MOSFETs on SOI technology at millimeter-wave frequencies, towards material properties extraction and device figures of merit assessment. It also includes circuit design to analyze substrate related performance and features at circuit level. His research involves as well advanced on-wafer calibration and de-embedding techniques for accurate characterization at millimeter-wave and sub-millimeter-wave frequencies.

Research Projects

  • Ultra-wideband (100 kHz to 110 GHz) characterization and model extraction of advanced FD-SOI MOSFET: complete small-signal equivalent circuit including
    • Advanced Self-Heating characterization
    • Substrate and Back-Gate networks modelling
  • mm-wave IC design
      • 28 & 39 GHz dual-band PAs for 5G applications
      • 39 GHz LNA
  • On-wafer RF up to 110 GHz calibration measurements
    • Custom calibration kit design and characterization
    • Analysis of residual probe-dependent errors
    • Evaluation of calibration reference impedance
  • RF material property extraction
  • Silicon-based substrate modelling and development
    • RF-SOI: High Resistivity and Trap-Rich
    • PN junction-enhanced RF-Si substrates
    • Gold-doped Si
    • GaN on Si
    • Porous Silicon

Publications

Awards

  1. EuMIC Young Engineer Prize award at the European Microwave Integrated Circuits Conference 2019, for the paper:
    L. Nyssens, M. Rack, and J.-P. Raskin, “Effective Resistivity Extraction of Low-Loss Silicon Substrate at Millimeter-Wave Frequencies,” in 2019 14th European Microwave Integrated Circuits Conference (EuMIC), 2019, pp. 1–4. doi: 10.23919/EuMIC.2019.8909575.

PhD Dissertation

  1. L. Nyssens, “A systemic analysis of silicon substrates toward improvements of integrated FD-SOI circuits performance at mm-wave frequencies,” Ph.D. dissertation, 2023. [Online]. Available: http://hdl.handle.net/2078.1/277786.

Book Chapters

  1. L. Nyssens, M. Rack, and J.-P. Raskin, “Chapter 2 – FD-SOI and RF-SOI technologies for 5G,” in New Materials and Devices Enabling 5G Applications and Beyond, ser. Materials Today, N. Collaert, Ed., Elsevier, 2024, pp. 33–55, isbn: 978-0-12-822823-4. doi: 10.1016/B978-0-12-822823-4.00002-9. [Online]. Available: https://www.sciencedirect.com/science/article/pii/B9780128228234000029.
  2. L. Nyssens, M. Rack, and J.-P. Raskin, “Chapter 9 – circuits for 5G applications implemented in FD-SOI and RF/PD-SOI technologies,” in New Materials and Devices Enabling 5G Applications and Beyond, ser. Materials Today, N. Collaert, Ed., Elsevier, 2024, pp. 275–316, isbn: 978-0-12-822823-4. doi: 10.1016/B978-0-12-822823-4.00009-1. [Online]. Available: https://www.sciencedirect.com/science/article/pii/B9780128228234000091.

Conference Proceedings

  1. M. Rack, D. Lederer, L. Nyssens, A. Paganini, M. B. Shinde, A. Beganovic and J.-P. Raskin, “Device layout dimension impact on substrate effective resistivity”, 2018 S3S Conference,San Francisco, CA, Oct. 2018, pp. 1-2, doi: 10.1109/S3S.2018.8640211.
  2. L. Nyssens, M. Rack and J.-P. Raskin, “New method for accurate transmission line characterization on low-loss silicon substrate at millimeter-wave frequencies”, Microwave Technology and Techniques Workshop, ESA-ESTEC, Noordwijk, The Netherlands, Apr.2019.
  3. M. Rack, L. Nyssens and J.-P. Raskin, “Silicon-substrate enhancement technique enabling high-quality integrated RF passives”, 2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, June 2019, pp. 1295-1298, doi: 10.1109/MWSYM.2019.870109.
  4. G. Scheen, R. Tuyaerts, M. Rack, L. Nyssens, J. Rasson and J.-P. Raskin, “Post-process local porous silicon integration method for RF application”, 2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, June 2019, pp. 1291-1294, doi: 10.1109/MWSYM.2019.8700844.
  5. G. Scheen, R. Tuyaerts, M. Rack, L. Nyssens, J. Rasson and J. Raskin, “Post-process porous silicon for 5G applications,” 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Grenoble, France, 2019, pp. 1-2, doi: 10.1109/EUROSOI-ULIS45800.2019.9041906. Award: Best Paper.
  6. L. Nyssens, A. Halder, …, J.-P. Raskin, V. Kilchytska, “Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures,” ESSDERC 2019 – 49th European Solid-State Device Research Conference (ESSDERC), Cracow, Poland, 2019, pp. 162-165, doi: 10.1109/ESSDERC.2019.8901704.
  7. L. Nyssens, M. Rack and J. Raskin, “Effective Resistivity Extraction of Low-Loss Silicon Substrate at Millimeter-Wave Frequencies,” 2019 14th European Microwave Integrated Circuits Conference (EuMIC), Paris, France, 2019, pp. 1-4, doi: 10.23919/EuMIC.2019.8909575. Award: Best Young Engineer Paper.
  8. L. Nyssens, A. Halder, B. K. Esfeh, N. Planes, D. Flandre, V. Kilchytska and J.-P. Raskin, “28 FDSOI RF Figures of Merit down to 4.2 K,” in Proceedings of the 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), San Jose, CA, USA, 2019, pp. 1-3, doi: 10.1109/S3S46989.2019.9320656.
  9. V. Kilchytska, S. Makovejev, B. Kazemi Esfeh, L. Nyssens, A. Halder, J.-P. Raskin, D. Flandre, “Electrical characterization of advanced MOSFETs towards analog and RF applications,” 2020 IEEE Latin America Electron Devices Conference (LAEDC), San Jose, Costa Rica, 2020, pp. 1-4, doi: 10.1109/LAEDC49063.2020.9073536.
  10. S. Wane, V. Huard, M. Rack, L. Nyssens, …, J.-P. Raskin, “Broadband Smart mmWave Front-End-Modules in Advanced FD-SOI with Adaptive-Biasing and Tuning of Distributed Antenna-Arrays,” 2020 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS), Waco, TX, USA, 2020, pp. 1-5, doi: 10.1109/WMCS49442.2020.9172398.
  11. M. Rack, L. Nyssens, S. Wane, D. Bajon and J. -P. Raskin, “DC-40 GHz SPDTs in 22 nm FD-SOI and Back-Gate Impact Study,” 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Los Angeles, CA, USA, 2020, pp. 67-70, doi: 10.1109/RFIC49505.2020.9218317. 
  12. A. Halder, L. Nyssens, M. Rack, J. -P. Raskin and V. Kilchytska, “Effect of Heat Sink in Back-End of Line on Self-Heating in 22 nm FDSOI MOSFETs,” 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Caen, France, 2020, pp. 1-4, doi: 10.1109/EUROSOI-ULIS49407.2020.9365293.
  13. M. Vanbrabant, L. Nyssens, V. Kilchytska and J. -P. Raskin, “Assessment of RF compact modelling of FD SOI transistors,” 2021 IEEE Latin America Electron Devices Conference (LAEDC), Mexico, Mexico, 2021, pp. 1-3, doi: 10.1109/LAEDC51812.2021.9437955.
  14. M. Rack, L. Nyssens, S. Wane, D. Bajon, D. Lederer and J. -P. Raskin, “FD-SOI mm-Wave Differential Single-Pole Switches with Ultra-High Isolation,” 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, 2021, pp. 1-2, doi: 10.1109/VLSI-TSA51926.2021.9440095.
  15. L. Nyssens, M. Rack, A. Halder, M. Vanbrabant, V. Kilchytska, and J.-P. Raskin, “Back-Gate Network Extraction Free from Dynamic Self-Heating in FD SOI,” in 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021, pp. 1–2. doi: 10.1109/VLSI-TSA51926.2021.9440125.
  16. M. Rack, L. Nyssens, M. Nabet, D. Lederer and J. -P. Raskin, “Field-Effect Passivation of Lossy Interfaces in High-Resistivity RF Silicon Substrates,” 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), Caen, France, 2021, pp. 1-4, doi: 10.1109/EuroSOI-ULIS53016.2021.9560697. 
  17. M. Rack, L. Nyssens, Q. Courte, D. Lederer and J. -P. Raskin, “Impact of Device Shunt Loss on DC-80 GHz SPDT in 22 nm FD-SOI,” ESSDERC 2021 – IEEE 51st European Solid-State Device Research Conference (ESSDERC), Grenoble, France, 2021, pp. 195-198, doi: 10.1109/ESSDERC53440.2021.9631835.
  18. S. Wane, …, L. Nyssens et al., “High Resolution Spintronics Probe-Array Technology Solutions for Very Near-Field Scanning,” 2021 IEEE Conference on Antenna Measurements & Applications (CAMA), Antibes Juan-les-Pins, France, 2021, pp. 241-246, doi: 10.1109/CAMA49227.2021.9703656.
  19. A. Halder, L. Nyssens, M. Rack, D. Lederer, V. Kilchytska and J. -P. Raskin, “22 nm FD-SOI MOSFET Figures of Merit at high temperatures upto 175 °C,” 2022 IEEE 22nd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Las Vegas, NV, USA, 2022, pp. 27-30, doi: 10.1109/SiRF53094.2022.9720052.
  20. M. Rack, L. Nyssens et al., “High-Resistivity Substrates with PN Interface Passivation in 22 nm FD-SOI,” 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, 2022, pp. 1-2, doi: 10.1109/VLSI-TSA54299.2022.9771028.
  21. M. Rack, L. Nyssens, Q. Courte, D. Lederer and J. -P. Raskin, “A DC-120 GHz SPDT Switch Based on 22 nm FD-SOI SLVT NFETs with Substrate Isolation Rings Towards Increased Shunt Impedance,” 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Denver, CO, USA, 2022, pp. 83-86, doi: 10.1109/RFIC54546.2022.9863217.
  22. S. Wane, …, L. Nyssens et al., “Energy-Efficient RF-Optics Multi-Beam Systems Using Correlation Technologies: Toward Hybrid GaN-FDSOI Front-End-Modules,” 2022 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS), Waco, TX, USA, 2022, pp. 1-6, doi: 10.1109/WMCS55582.2022.9866246.
  23. L. Nyssens, M. Rack, D. Lederer and J. -P. Raskin, “Effect of probe coupling on MOSFET series resistance extraction up to 110 GHz,” 2022 IEEE Latin American Electron Devices Conference (LAEDC), Cancun, Mexico, 2022, pp. 1-4, doi: 10.1109/LAEDC54796.2022.9908195.
  24. M. Nabet, M. Rack, L. Nyssens, J. -P. Raskin and D. Lederer, “28 GHz Down-Conversion Mixer with RF Back-Gate Excitation Topology in 22-nm FD-SOI,” 2022 17th European Microwave Integrated Circuits Conference (EuMIC), Milan, Italy, 2022, pp. 296-299, doi: 10.23919/EuMIC54520.2022.9923503.
  25. L. Nyssens et al., “A 2.5-2.6 dB Noise Figure LNA for 39 GHz band in 22 nm FD-SOI with Back-Gate Bias Tunability,” 2022 17th European Microwave Integrated Circuits Conference (EuMIC), Milan, Italy, 2022, pp. 60-63, doi: 10.23919/EuMIC54520.2022.9923552.
  26. L. Nyssens et al., “PN Junctions Interface Passivation in 22 nm FDSOI for Low-Loss Passives,” 2022 24th International Microwave and Radar Conference (MIKON), Gdansk, Poland, 2022, pp. 1-4, doi: 10.23919/MIKON54314.2022.9924803.
  27. S. Wane, …, L. Nyssens et al., “Combined Thermo-Reflectance and Thin-Film Coating in Near-Field Imaging of Chip-Package-PCB-Antenna Modules for Industrial-Testing and Failure Analysis,” 2023 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS), Waco, TX, USA, 2023, pp. 1-6, doi: 10.1109/WMCS58822.2023.10194284. 
  28. L. Nyssens, M. Rack, R. Tuyaerts, D. Lederer and J. -P. Raskin, “Verification of Reference Impedance from Common On-Wafer Calibrations on Commercial Calibration Substrates,” 2023 101st ARFTG Microwave Measurement Conference (ARFTG), San Diego, CA, USA, 2023, pp. 1-4, doi: 10.1109/ARFTG57476.2023.10278758.
  29. M. Rack, L. Nyssens et al., “A Compact 120 GHz LNA in 22 nm FD-SOI with Back-Gate Controllable Variable-Gain,” 2023 18th European Microwave Integrated Circuits Conference (EuMIC), Berlin, Germany, 2023, pp. 386-389, doi: 10.23919/EuMIC58042.2023.10288898.
  30. S. Ma, L. Nyssens, J. -P. Raskin and D. Lederer, “Sub-mmWave Transmission Lines on Silicon-Based Technologies,” 2023 53rd European Microwave Conference (EuMC), Berlin, Germany, 2023, pp. 42-45, doi: 10.23919/EuMC58039.2023.10290173.

Journal Papers

  1. N. André, M. Rack, L. Nyssens, C. Gimeno, D. Oueslati, K. Ben Ali, S. Gilet, C. Craeye, J.-P. Raskin and D. Flandre, “Ultra Low-Loss Si Substrate for On-Chip UWB GHz Antennas”, IEEE Journal of the Electron Devices Society, vol. 7, pp. 393-397, Mar. 2019, doi: 10.1109/JEDS.2019.2902636.
  2. M. Rack, L. Nyssens, and J.-P. Raskin, “Low-loss Si-substrates enhanced using buried PNjunctions for RF applications”, IEEE Electron Device Letters, vol. 40, pp. 690-693, May 2019, doi: 10.1109/LED.2019.2908259.
  3. G. Scheen, R. Tuyaerts, M. Rack, L. Nyssens, J. Rasson, M. Nabet and J.-P. Raskin, “Post-process porous silicon RF 5G applications”, Solid-State Electronics, vol. 168, pp. 107719, ISSN 0038-1101, 2020, doi: 10.1016/j.sse.2019.107719.
  4. L. Nyssens, M. Rack and J.-P. Raskin, “Effective Resistivity Extraction of Low-Loss Silicon Substrate at Millimeter-Wave Frequencies”, International Journal of Microwave and Wireless Technologies, vol. 12, no. 7, pp. 615-628, 2020, doi: 10.1017/S175907872000077X.
  5. L. Nyssens, A. Halder, B. K. Esfeh, N. Planes, D. Flandre, V. Kilchytska and J.-P. Raskin, “28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K,” in IEEE Journal of the Electron Devices Society, vol. 8, pp. 646-654, 2020, doi: 10.1109/JEDS.2020.3002201.
  6. L. Nyssens, A. Halder, B. Kazemi Esfeh, N. Planes, D. Flandre, V. Kilchytska and J.-P. Raskin, “Self-Heating in FDSOI UTBB MOSFETs at Cryogenic Temperatures and its Effect on Analog Figures of Merit,” in IEEE Journal of the Electron Devices Society, vol. 8, pp. 789-796, 2020, doi: 10.1109/JEDS.2020.2999632.
  7. V. Kilchytska, S. Makovejev, B. Kazemi Esfeh, L. Nyssens et al., “Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications,” in IEEE Journal of the Electron Devices Society, vol. 9, pp. 500-510, 2021, doi: 10.1109/JEDS.2021.3057798.
  8. L. Nyssens, M. Rack, A. Halder, J. . -P. Raskin and V. Kilchytska, “On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET,” in IEEE Electron Device Letters, vol. 42, no. 5, pp. 665-668, May 2021, doi: 10.1109/LED.2021.3071272.
  9. M. Vanbrabant, L. Nyssens, V. Kilchytska and J. -P. Raskin, “Back-Gate Lumped Resistance Effect on AC Characteristics of FD-SOI MOSFET,” in IEEE Microwave and Wireless Components Letters, vol. 32, no. 6, pp. 704-707, June 2022, doi: 10.1109/LMWC.2022.3162497.
  10. L. Nyssens, M. Rack, C. Schwan, Z. Zhao, et al., “Impact of substrate resistivity on spiral inductors at mm-wave frequencies,” Solid-State Electronics, vol. 194, p. 108 377, 2022. doi: 10.1016/j.sse.2022.108377. 
  11. L. Nyssens, M. Rack, M. Nabet, C. Schwan, et al., “High-Resistivity with PN Interface Passivation in 22 nm FD-SOI technology for Low-Loss Passives at RF and Millimeter-Wave Frequencies,” Solid-State Electronics, vol. 205, p. 108 656, 2023. doi: 10.1016/j.sse.2023.108656.
  12. L. Nyssens, S. Ma, M. Rack, D. Lederer and J. -P. Raskin, “Probe-Dependent Residual Error Analysis for Accurate On-Wafer MOSFET Measurements up to 110 GHz,” in IEEE Journal of the Electron Devices Society, vol. 11, pp. 650-657, 2023, doi: 10.1109/JEDS.2023.3284291.
  13. A. Halder et al., “Impact of High Temperature Up to 175 °C on the DC and RF Performances of 22-nm FD-SOI MOSFETs,” in IEEE Transactions on Electron Devices, vol. 70, no. 10, pp. 4987-4992, Oct. 2023, doi: 10.1109/TED.2023.3303150.