News Description

5^th Reconfigurable Market Seminar

October 2nd, 2018

Salle académique, University of Mons, 31 Bld. Dolez, Mons, Belgium

PDF: https://tinyurl.com/ydfks8up

Free registration: https://tinyurl.com/ybjocmqp

Reconfigurable hardware is among us and its role is gaining importance in the most evolving markets. Although relegated in the past to hardware specialists and designers, today reconfigurable devices seem to be conquering a variety of sectors for many reasons. From big data to artificial intelligence, from software developers to cloud analysts, from new IT paradigms to ASICs, the market is evolving not only because of speed, but also by the need of green IT strategies. Indeed, big players like Amazon, Google, Microsoft and Intel are now merging initiatives with Altera (today Intel) and Xilinx, producing heterogeneous architectures and novel processing devices such as TPUs and VPUs.

We would like to follow and embrace this momentum. For this reason, this seminar is dedicated to meet specialists from academia and industry to discuss about their needs and solutions that reconfigurable hardware can bring. It is also an invitation to see novel strategies to grow this market. As example, see some topics of interest that will be discussed:

·       New paradigms for reconfigurable and communication-centric computing

·       Artificial intelligence and deep learning: languages, models, architectures and platforms

·       Cloud and HPC platforms and architectural strategies

·       Edge Computing, reconfigurable and adaptive embedded SoCs

·       Low power reconfigurable and multiprocessor SoCs

·       OS and middleware for reconfigurable, heterogeneous and multicore SoCs

·       Specification languages, OS and design methodologies

·       Industrial case studies and needs

Invited Speakers

·       Nicolas HUOT, ANTWERSPACE. Usage of reconfigurable electronics in modern high-reliability communication equipment        

Presentation of the usage of reconfigurable electronics throughout Antwerp Space's line of modem products including space flight electronics

Bio. digital micro-electronics engineer by training, I have worked for more than 4 years at ARM ltd, then moved to Belgium and worked 2 years at Barco Silex. For more than 5 years I am a system engineer at Antwerp Space, working on space flight equipments mostly.

·       Johan Deben, AVNET.EU. Adaptive Machine Learning Acceleration with Xilinx FPGAs/SOCs

This presentation will introduce you to the implementation of Machine Learning Networks in FPGA and SOC devices.  

·       Frédéric Leens, Exostiv Labs. (To be provided later)

 ·       Ramses Valvekens, EASICS.BE. Automated optical inspection (AOI) of Printed Circuit Boards (PCB) using deep learning on FPGA           

Automated optical inspection (AOI) of printed circuit boards (PCB) is a critical step in assuring the quality of assembled boards. Pinpointing defects in this step and correcting them is far better than doing so later on, during electrical testing, or worse in the field. The large variety of electronic components makes it hard to keep AOI software up to date. Deep learning is therefore ideally suited for this task. The speaker demonstrates how easics does this using FPGA technology, using a scalable solution. It takes advantage of ever increasing FPGA computational power and keeps up with component diversity into the future.

Bio. Ramses Valvekens is managing director of Easics. He also remains active as a systems architect, focusing on technology selection, project risk reduction and cost-effective mixed-signal ASIC and FPGA design trade-offs. He is a regular speaker at industry conferences and gives lectures in semiconductor system design. He holds a Master degree (1997) in Electronics Engineering from the Katholieke Universiteit Leuven. He performed research in signal processing at the Lawrence Livermore National Laboratories (California, USA) and at the Institut National Polytechnique de Grenoble (France). In 1994, he won the Barco/VIK prize for the design of an FPGA-based reconfigurable processor for industrial image processing in cooperation with imec . He has been working at Easics since 1997. During the TranSwitch years (2000 till 2004), he was technical manager of a product family of mixed-signal telecom chips. He received the TranSwitch Employee Recognition Award in 2003 and is co-inventor of two telecommunication patents.

·       Jahanzeb Ahmad, INTEL           (To be provided later)                    

·       Prof. Fritz Mayer-Lindenberg, Institute of Embedded Systems, TUHH, Hamburg, Germany, A Paradigm for the Design of Scalable FPGA based Numeric Processors

The proposed system architecture is networks of standard and soft processors on networks of FPGA or SoC chips. Application programming mostly becomes parallel and distributed processor programming, and systems are composed of predefined, separately designed circuit components. A HW operating system is proposed covering the off-chip networking and the interfacing of the on-chip processors, and (re-)configuration. The approach imposes special requirements on the programming tools to be used. Prototypical designs and implementations of the HW OS and suitable PL exist.

Bio. Retired full professor at the TU Hamburg, former head of the institute of Computer Technology.

·       Prof. Nele Mentens, KU Leuven. Configurable computing for cryptographic implementations

The security strength and the implementation security of cryptographic algorithms are continuously analyzed and improved. Therefore, cryptographic agility is desirable, i.e. the ability of cryptographic algorithms and implementations to cope with changing attack scenarios and security requirements. In this talk, cryptographic agility is addressed from the implementation perspective, namely through configurable computing. The talk will cover both commercial off-the-shelf and application-specific configurable computing platforms. The differences in design approach and efficiency will be discussed.

Bio. Nele Mentens received her master and Ph.D. degree from KU Leuven in 2003 and 2007, respectively. Her Ph.D. focused on secure and efficient coprocessor design for cryptographic applications on FPGAs. Currently, Nele is an associate professor at KU Leuven. Her research interests are in the domains of reconfigurable platforms for security applications, design automation for cryptographic hardware and security in constrained environments. Nele was a visiting researcher for 3 months at the Ruhr University Bochum in 2013 and at EPFL in 2017. She was/is the PI in around 15 finished and ongoing research projects with national and international funding. She served as a reviewer for many international conferences and journals and was/is part of the program committee of around 50 international conference editions. Nele is (co-)author in approximately 100 publications in international journals, conferences and books.