News Description

Subthreshold Source-Coupled Circuit Design for Ultra-Low-Power Applications.

In this talk, a novel approach is presented for implementing ultra-low-power digital and mixed-signal components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18um and 90nm technologies show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ per gate.

Complex digital blocks such as parallel / pipelined adders and multipliers designed by using the STSCL topology will be presented - as well as some examples of mixed-signal blocks, e.g. ultra-low power A/D converters.

Pr. Yusuf Leblebici biography is available on the EPFL website.