logo
WP4 Capcitor-less Implantable Stimulation
line
Home

WP1 Metalisation

WP2 Connection

WP3 Amplifier

WP4 Stimulation

WP5 Fabrication

WP6 Assembly

WP7 Models

WP8 Global System

Description

Electronic aspects

Conventional nerve stimulators employ blocking capacitors in series with the electrodes. These serve two purposes: 1) to ensure that the mean current is zero (charge balnce) in normal operation and, 2) to ensure that no direct current flows, which would cause electrolysis under fault conditions (semiconductor device failure). Although a stimulator without blocking capacitors can pass very little direct current, nevertheless blocking capacitors are used in implanted stimulators because of the protection they provide under possible fault conditions. In practice, the blocking capacitors are large (a few µF), and as the integrated circuits get smaller with developments in semiconductor technology, the amount of the implanted stimulator that is occupied by these capacitors becomes increasingly large. This problem is particularly pronounced for the Active Cuff, the topic of this proposal, in which no blocking capacitors can be incorporated. In general, if the blocking capacitors were eliminated, in addition to reductions in area there would be another concomitant advantage: that no voltage drop would be wasted across them. Thus, the required power supply voltage would be lower, which in turn would result in significant reduction of the total power consumption of the implant and improvement in the power efficiency of the stimulator.

Biological aspects

Besides, better understanding for the physiological reactions of nerve tissues in respond to stimulation is obligatory for saftey management of the resultant implants. 

WP32

Achievement

One of the main technological challenges in the IMANE project is miniaturization of the physical size of the implantable neural stimulator. Conventional neural stimulators use external off-chip capacitors (see Fig. 1) for DC protection in the event of semiconductor failure. For a multi-channel stimulator, the use of these external capacitors results in large physical volume. WP4 tackled this problem by proposing a novel high-frequency current-switching (HFCS) stimulation scheme. The technique allows the blocking capacitors to be integrated on chip alongside with the rest of the stimulator circuitry, hence achieving full system integration.

The novel HFCS resulted in the world's first fail-safe fully-integrated neural stimulator (see Fig. 2). Two different prototype stimulators using the HFCS technique have been fabricated so far. The modular structure of the ASIC allows the construction of a multi-channel stimulation and recording system by simply connecting multiple ASICs together. For the prototype stimulator ASIC, the stimulation parameters have been optimized for the IMANE project, which mainly focuses on vagus nerve stimulation. However, the novel circuit techniques developed in WP4 (e.g., HFCS, new current generator circuit, etc) can be easily used for other neural stimulation applications, such as retinal, cochlear and nerve root stimulators, offering mass volume reduction.

The prototype stimulator ASIC using HFCS has been successfully evaluated both in-vitro and in-vivo. The stimulator ASIC conforms to the requirement of fail-safe under single-failure conditions. The measured DC leakage current using this stimulator was characterised with Platinum electrodes in a saline tank, and was found to be well below the current safety limit. The size reduction and full-system integration offered by the novel stimulator ASIC also benefits other parts of the implant design chain, such as more flexibility in packaging, reduced cost, minimized cross-talk between components and enhanced reliability.

Publication

  1. X. Liu and A. Demosthenous, "A Fail-safe ASIC for Implantable Neural Stimulation," in Proceedings of 33rd European Solid-State Circuits Conference (ESSCIRC), pp. 460-463, Germany, Sept. 2007.
  2. X. Liu, A. Demosthenous, Mohamad Rahal and Nick Donaldson, "Recent Advances in the Design of Implantable Stimulator Output Stages," in Proceedings of European Conference on Circuit Theory and Design (ECCTD), Spain, Aug. 2007.
  3. X. Liu, A. Demosthenous and N. Donaldson, "Implantable Stimulator Failures: Causes, Outcomes, and Solutions," in Proceedings of 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBS), pp. 5786-5789, France, Aug. 2007.
  4. X. Liu, A. Demosthenous and N. Donaldson, “A Safe Transmission Strategy for Power and Data Recovery in Biomedical Implanted Device,” in Proceedings of 2007 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2367-2370, May 2007, US.
  5. X. Liu, A. Demosthenous and N. Donaldson, “A Fully Integrated Fail-safe Stimulator Output Stage Dedicated to FES Stimulation,” in Proceedings of 2007 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2076-2079, May 2007, US.

 

 

wp41
Figure 1. A conventional nerve root stimulator



WP42

Figure 2 A fully integrated fail-safe stimulator ASIC by EEL
lines
éditeur responsable : GREN, Faculté de Médecine, UCL 54.46, Université catholique de Louvain
adresse : 54 Avenue Hippocrate 54, 1200 Bruxelles (Belgique) - Tél: +32 (0)2 764 54 45 - Fax: +32 (0)2 764  94 22

|vie privée| règlements Document made with KompoZer