Course Description

Ultra-low-power design of digital, analog and RF circuits

 

May 26th, 2008

Christian Enz, CSEM & EPFL, Switzerland

Georges Gielen, Katholieke Universiteit Leuven, Leuven, Belgium

Naveen Verma, Massachusetts Institute of Technology, Cambridge, MA, USA

David Bol, Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium

Denis Flandre, Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium

Ultra Low-Power MEMS-based Radio for Wireless Sensor Networks  (C. Enz)

The recent advances made in MEMS and particularly in RF MEMS technology are enabling new architectures for the integration of RF transceivers with improved performance and smaller size. Several fundamental building blocks benefit from the availability of high-Q resonators in the RF front-end, the analog baseband and the frequency synthesizer to lower power consumption, phase noise and die area. In addition, the compatibility of MEMS with CMOS opens the door to a higher integration level using for example an above-IC approach.  This paper presents the recent work made at CSEM in the field of ultra low-power transceiver for wireless sensor network applications

Ultra Low-Power Analog Circuits (G. Gielen)

Many mobile and wireless applications today require ultra low power design techniques.
This tutorial will explain some techniques for power minimization in analog circuits and will illustrate this with some practical designs.

Low-Voltage System Design for Highly Energy-Constrained Applications  (N. Verma)

Ultra-low-power electronics is forging brand new applications including sophisticated biomedical implants, ubiquitous sensor networks, and portable multimedia devices. To enable these highly energy-constrained systems, low-voltage circuits are critical, but they require special considerations with regards to process variation, power delivery, system architecture, technology optimization, and mixed-signal components.  This tutorial treats all of these by providing an analytical development and practical examples

Technology Scaling for Ultra-Low-Power Digital Circuits – Is Mainstream Technology Adapted to Special Design (D. Bol - UCL)

Ultra-low-power circuits  have become an emerging trend in VLSI for applications such as microsensors, biomedical dev ices or RFID's.  As ultra-low power design involves scaling supply voltage to extremely low values as low as 0.2V, it raises several robustness and performance issues.  At the same time, technology scaling trend targets mainstream high-performance aplpications with dramaticincrease of  short-channel effects, leakage current and process variability.  It is thus not clear whether ultra-low-power circuits benefit  from scaling trend dictated by Moore's law.  In this tutorial, the interests and limitations of technology scaling for ultra-low-power design are investigated down to 32-nm node with predictive technology models.  Design techniques are presented to increase robustness and energy efficiency at smallest technology nodes.

Novel Ultra-Low-Power Design Techniques for Analog, Digital and Memory Functions - Implementations in SOI Technology (D. Flandre)

 The ultra-low-power (ULP) System-on-chip integration of different circuit functions (analog, digital, memory, and possibly sensors) is a major present and future challenge. Some important outcomes are:
- the very significant increase of static power and the drastic reduction of noise margins which affect all types of circuits, but above all, SRAM,
- the lesser resistance to extended temperature operation ranges,
- new applications such as those including energy scavenging or wireless power transfer.
Numerous solutions are proposed to tackle these issues, among which subthreshold operation, clock frequency optimisation, new architecture developments (e.g., 10 transistors SRAM cells), higher performance CMOS processes (such as Silicon-on-Insulator) or with multiple threshold voltages (enabling supply gating as in MTCMOS).

Venue

The course will take place in the More building  (auditoire More 53). According to the map available here :

• Nr. 12 in square Q7 is where the course will be held.
• For people coming by train, the "Louvain-la-Neuve-univ." station is in square D6-7.

Programme

09h00 : Ch. Enz (EPFL)

10h30 : Coffee break

11h00 : G. Gielen (KULeuven)

12h30 : Lunch time

14h00 : N. Verma (MIT)

14h45 : D. Bol (UCL)

15h30 : Coffee break

16h00 : D. Flandre (UCL)

17h45 : end of the tutorial