Title: "Hardware architecture for machine learning and image processing"
Note: Joint ISP Group and ECS Group
Speaker: Martin Lefebvre (ECS Group, ICTEAM, UCL)
Location: "Shannon" Seminar Room, Place du Levant 3, Maxwell Building, 1st floor
Date / Time (duration): Thursday 29/03/2018, 16h15 (~45')
Abstract: For some decades, efficient machine learning and image processing algorithms have been successfully developed to achieve a broad range of tasks, e.g. prediction, classification, compression, ... However, the hardware used for running those algorithms used to be inefficient, both in terms of computational performance and power consumption. In this seminar, we focus on the state-of-the-art implementation of electronic circuits making use of such algorithms. In particular, computational CMOS image sensors and deep- and machine learning processors are discussed. On the one hand, imagers focus on reducing the amount of data produced by the sensor either by performing in-pixel or embedded processing of the image, based on techniques such as edge detection, feature extraction, or compressive sensing. On the other hand, some cutting-edge deep- and machine learning processors rely on analog computations performed inside SRAM memories, to reduce the power consumption related to memory accesses and to increase the performance through parallelism, thus improving the energy efficiency of those processors.
Last updated March 28, 2018, at 08:51 AM