MUSICS: Graduate School on MUltimedia, SIlicon, Communications, Security : Electrical and Electronics Engineering

Graduate School on MUltimedia, SIlicon, Communications, Security: Electrical and Electronics Engineering

News Description

( current | all | 2024 | 2023 | 2022 | 2021 | 2020 | 2019 | 2018 | 2017 | 2016 | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009 | 2008 | 2007 | 2006)

The SMALL Research Group invites you cordially to the following research seminar:

 

Recent packaging technologies for semiconductors and MEMS

Speaker: Dr. Bradford J. Factor, ASE Europe

When/where: November 24th, 2012, 3.00 PM, Aula SUD07 (Place Croix du Sud - square E8 on the map http://www.uclouvain.be/cps/ucl/doc/adpi/documents/PLAN_2007recto.pdf)


Abstract

Semiconductor assembly and test, often known as "packaging" is an integral part of the overall manufacturing process for semiconductor components. In this talk, a short history of semiconductor packaging will be presented along with a description of common package types and associated manufacturing processes. Over the past 20 years, the number of available package types has increased dramatically - with the availability both simple and complex new package concepts. The talk will conclude with a discussion of packaging technologies used in micromechanical (MEMS) and sensor devices which are relavant to the MEMS design.

About the speaker:

Bradford Factor received his Ph.D in 1991 from Stanford University in Applied Physics. After this, he held research fellowships in France and Greece and at the polymers division of NIST in the United States.

Bradford started working in the semiconductor industry in 1995 - first at Intel's Advance Package Technology Development team in 1995 and then Lucent Microelectronics in 1999 to work on advanced materials and flip chip interconnection. He joined ASE Europe in 2002 and is currently Director of Packaging Technology. Supporting ASE's European customer base, he focuses on new technologies in ASE Group including Cu Wire Bonding, Flip Chip Packaging, Wafer Level Packaging as well as Power Packaging. He is involved in several industry organizations such as ITRS Assembly & Packaging Working Group, IEEE CMPT and IMAPS France.

He has received several patents and has published several journal articles.































 

Page last modified on May 29, 2015, at 04:54 PM