RF SOI Group https://sites.uclouvain.be/RF-SOI-group UCLouvain RF SOI Raskin Rack Substrate Measurements mm-wave Wed, 10 Jun 2020 11:50:08 +0000 en-US hourly 1 https://sites.uclouvain.be/RF-SOI-group/wp-content/uploads/2025/05/cropped-Logo_RFSOI_MidQ-crop-32x32.png RF SOI Group https://sites.uclouvain.be/RF-SOI-group 32 32 martinrack https://sites.uclouvain.be/RF-SOI-group/team-martinrack/ https://sites.uclouvain.be/RF-SOI-group/team-martinrack/#respond Tue, 09 Jun 2020 17:27:35 +0000 https://sites.uclouvain.be/RF-SOI-group/?p=1203

Martin Rack

Martin Rack is a PhD student from Université catholique de Louvain, Beglium.

His main interests are substrate modeling, characterization and optimization towards successful monolithic integration of RF devices using silicon technology.

To that end he is involved in the complete small-signal modeling of large substrate volumes for the evaluation of substrate crosstalk interference between circuit nodes.

He is also implicated in the development of large-signal models of the non-linear behavior of semiconductor substrate interfaces for the evaluation of substrate-induced harmonic distortion in RF systems.

Research Projects

  • Non-linear large-signal RF substrate modelling
  • mm-wave IC design
      • 28 GHz switches
      • 39 GHz LNA
  • On-wafer RF & mm-wave measurements
  • RF material property extraction

 

  • Silicon-based substrate modelling and development
      • RF-SOI: High Resistivity and Trap-Rich
      • PN junction-enhanced RF-Si substrates
      • Gold-doped Si
      • GaN on Si
      • Porous Silicon

Publications

Conference Proceedings

  1. M. Rack, K. Ben Ali, J.-P. Raskin, X. Sun, C. Roda Neve, G. Van der Plas and M. Stucchi, “Modeling of anomalous CV curves in TSVs after wafer thinning”, Program Technical Week – PTW2014, IMEC, Leuven, Belgium, October 2014.
  2. X. Sun, A. Rouhi Najaf Abadi, W. Guo, K. Ben Ali, M. Rack, C. Roda Neve, M. Choi, V.Moroz, I. De Wolf, J.-P. Raskin, G. Van der Plas, E. Beyne and P. Absil, “Noise couplingbetween TSVs and active devices: planar nMOSFETs vs. nFinFETs”, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, 2015, pp.260-265. Award: Outstanding session paper.
  3. M. Rack, M. Stucchi, X. Sun, C. Roda Neve, G. Van der Plas, E. Beyne, P. Absil and J.-P.Raskin, “Modeling the Effect of Charges in the Back Side Passivation Layer on ThroughSilicon Via (TSV) Capacitance after Wafer Thinning”, 2015 IEEE MTT-S International Microwave Symposium (IMS), Phoenix, AZ, 2015, pp. 1-4.
  4. Y. Belaroussi, A. Slimane, M. T. Belaroussi, M. Trabelsi, G. Scheen, M. Rack, J.-P. Raskin, “Caractérisation physique et dynamique du silicium poreux pour les applications RF”, 2ièmes journées Semiconducteurs et Oxyde Poreux, Montpellier, France, June 2015.
  5. M. Rack, X. Sun, C. Roda Neve, G. Van der Plas, M. Stucchi and J.-P. Raskin, “3D circuit model for TSV coupling including anomalous CV”, Program Technical Week – PTW2015, IMEC, Leuven, Belgium, October 2015.
  6. A. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, J.-P. Raskin, M. Rack, C. Roda Neve, M. Choi, V. Moroz, G. Van der Plas, I. De Wolf, E. Beyne and P. Absil, “Through Silicon Via to FinFET noise coupling in 3-D integrated circuits”, 2015 International Conferenceon IC Design & Technology (ICICDT), Leuven, 2015, pp. 1-4.
  7. M. Rack, X. Sun, G. Van der Plas, P. Absil, E. Beyne and J.-P. Raskin, “Fast and accurate modelling of large TSV arrays in 3D-ICs using a 3D circuit model validated against full-wave FEM simulations and RF measurements”, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 966-971.
  8. X. Sun, M. Rack, G. Van der Plas, M. Stucchi, J. De Vos, P. Absil, J.-P. Raskin and E. Beyne, “Investigation of TSV noise coupling in 3D-ICs using an experimental validated 3D TSV circuit model including Si substrate effects and TSV capacitance inversion behavior after wafer thinning”, 2016 IEEE MTT-S International Microwave Symposium (IMS), SanFrancisco, CA, 2016, pp. 1-4.
  9. M. Rack and J.-P. Raskin, “RF harmonic distortion modeling in silicon-based substrates including non-equilibrium carrier dynamics”, 2017 IEEE MTT-S International Microwave Symposium (IMS), Honolulu, HI, 2017, pp. 91-94. Award: Student Paper Competition Honorable Mention (4th place out of 394 participants)
  10. M. Rack and J.-P. Raskin, “Small- and large-signal RF modeling of silicon-based substrates”, MOS-AK Workshop, ESSDERC/ESSCIRC, Leuven, Belgium, 11-14 Sept. 2017.
  11. M. Rack, D. Lederer, L. Nyssens, A. Paganini, M. B. Shinde, A. Beganovic and J.-P. Raskin, “Device layout dimension impact on substrate effective resistivity”, 2018 S3S Conference,San Francisco, CA, Oct. 2018, pp. xx-yy.
  12. L. Nyssens, M. Rack and J.-P. Raskin, “New method for accurate transmission line characterization on low-loss silicon substrate at millimeter-wave frequencies”, Microwave Technology and Techniques Workshop, ESA-ESTEC, Noordwijk, The Netherlands, Apr.2019, pp. xx-yy.
  13. M. Rack, L. Nyssens and J.-P. Raskin, “Silicon-substrate enhancement technique enabling high-quality integrated RF passives”, 2019 IEEE MTT-S International MicrowaveSymposium (IMS), Boston, MA, June 2019, pp. xx-yy.
  14. G. Scheen, R. Tuyaerts, M. Rack, L. Nyssens, J. Rasson and J.-P. Raskin, “Post-process local porous silicon integration method for RF application”, 2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, June 2019, pp. xx-yy.
  15. M. Nabet, M. Rack, C.H. de Groot and J.-P. Raskin, “Behavior of Gold-Doped Siliconunder Small- and Large-RF Signal”, EuroSOI-ULIS, Grenoble, France, April 2019, pp.xx-yy.
  16. G. Scheen, R. Tuyaerts, L. Nyssens, M. Rack and J.-P. Raskin, “Ultra Low-Loss PorousSilicon Substrate for 5G applications”, EuroSOI-ULIS, Grenoble, France, April 2019, pp.xx-yy.Award:Best Paper.
  17. L. Nyssens, M. Rack and J.-P. Raskin, “Effective Resistivity Extraction of Low-LossSilicon Substrate at Millimeter-Wave Frequencies”, 49th European Microwave Conference(EuMC), Paris, France, Oct. 2019., pp. xx-yy.Award:Best Student Paper.
  18. M. Rack and J.-P. Raskin, “SOI Technologies for RF and Millimeter Wave Applications”, Electrochemical Society (ESC), Invited Paper, Atlanta, USA, October 2019, pp. xx-yy.
  19. A. Halder, L. Nyssens, M. Rack, J.-P. Raskin and V. Kilchytska, “Effect of Heat Sink in Back-End of Line on Self-Heating in 22nm FDSOI MOSFETs”, EuroSOI-ULIS, Caen,France, March 2020, pp. xx-yy.
  20. M. Rack and J.-P. Raskin, “SOI Devices and Substrates towards Millimeter Wave ICs”, 4th IEEE Electron Device Technology and Manufacturing (EDTM) Conference, Penang, Malaysia, March 2020, pp. xx-yy.
  21. E. Vandermolen, P. Ferrandis, F. Allibert, M. Nabet, M. Rack, Nur Zatil Ismah Hashimf, C.H. de Groot, J.-P. Raskin and M. Cassé, “Characterization of High Resistivity Au-Sisubstrates by Photo-Induced Current Transient Spectroscopy”, EuroSOI-ULIS, Leuven,Belgium, April 2020, pp. xx-yy.
  22. M. Rack, L. Nyssens, … , and J.-P. Raskin, “DC-40 GHz SPDTs in 22 nm FD-SOI and Back-Gate Impact Study”, Radio Frequency Integrated Circuits Symposium (RFIC), Los Angeles, USA, June 2020, pp. xx-yy.

Journal Papers

  1. Y. Belaroussi, M. Rack, A.A. Saadi, G. Scheen, M.T. Belaroussi, M. Trabelsi, J.-P. Raskin, “High quality silicon-based substrates for microwave and millimeter wave passive circuits”, Solid-State Electronics, vol. 135, pp. 78-84, Sept. 2017.
  2. B. Kazemi Esfeh, M. Rack, S. Makovejev, F. Allibert and J.-P. Raskin, “A SPDT RF Switch Small-and Large-signal Characteristics on TR-HR SOI Substrates”, IEEE Journalof the Electron Devices Society, vol. 6, pp. 543-550, Feb. 2018.
  3. M. Rack, Y. Belaroussi, K. B. Ali, G. Scheen, B. K. Esfeh and J. P. Raskin, “Small-and Large-Signal Performance Up To 175◦C of Low-Cost Porous Silicon Substrate for RF Applications”, IEEE Trans. Electron Devices, vol. 65, no. 5, pp. 1887-1895, May 2018.
  4. B. Kazemi Esfeh, M. Rack, F. Allibert and J.-P. Raskin, “RF Small- and Large-Signal Char-acteristics of CPW and TFMS Lines on Trap-Rich HR SOI Substrates”, IEEE Transactionson Electron Devices, vol. 65, no. 8, pp. 3120-3126, Aug. 2018.
  5. N. André, M. Rack, L. Nyssens, C. Gimeno, D. Oueslati, K. Ben Ali, S. Gilet, C. Craeye, J.-P. Raskin and D. Flandre, “Ultra Low-Loss Si Substrate for On-Chip UWB GHz Antennas”, IEEE Journal of the Electron Devices Society, vol. 7, pp. 393-397, Mar. 2019.
  6. M. Rack, L. Nyssens, and J.-P. Raskin, “Low-loss Si-substrates enhanced using buried PNjunctions for RF applications”, IEEE Electron Device Letters, vol. 40, pp. 690-693, May 2019.
  7. M. Nabet, M. Rack, Nur Zatil Ismah Hashim, C. H. de Groot, and J.-P. Raskin, “Behavior of Gold-Doped Silicon under Small- and Large-RF Signal”, Solid-State Electronics, vol.XX, no. X pp. xx-yy, XXX 2019.
  8. G. Scheen, R. Tuyaerts, M. Rack, L. Nyssens, J. Rasson and J.-P. Raskin, “Post-process local porous silicon integration method for RF application”, Solid-State Electronics, vol.XX, no. X pp. xx-yy, XXX 2019.
  9. L. Nyssens, M. Rack and J.-P. Raskin, “Effective Resistivity Extraction of Low-Loss SiliconSubstrate at Millimeter-Wave Frequencies”, lalalala, vol. XX, no. X pp. xx-yy, XXX 2020.

Book Chapters

  1. X. Sun, M. Rack, G. Van der Plas, J.-P. Raskin and E. Beyne, “Modeling and Characterization of TSV Induced Noise Coupling”, in “Noise Coupling in System-on-Chip”, 1st ed., T. Noulis, Ed. Boca Raton: CRC Press, 2017, pp. 195-232.
  2. M. Rack and J.-P. Raskin, “SOI Technology for RF and Millimeterwave Applications” in”Intelligent Nanosystems”, 1st ed., vol. 4, S. Deleonibus, Ed. Singapour??: Pan Stanford Publishing, 2019, pp. xxx-xxx

Patents

  1. M. Broekaart, F. Allibert, E. Desbonnet, J.-P. Raskin and M. Rack, “Procédé Pour Minimiser une Distorsion d’un Signal dans un Circuit Radiofréquence”, FR3066858, 30Nov. 2018.
  2. M. Rack and J.-P. Raskin, “Integrated Circuit Device and Method of Manufacturing Thereof”, WO2019211412, 7 Nov. 2019.
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